Project Results

  • component and system specifications
  • first achievements of dissemination, exploitation and standardization activities
  • first optical designs fabricated and measured
  • first electrical design in fabrication

…for more information, please see reports on deliverables page.

…further project results will be published soon.


WP6 – Dissemination, Exploitation and Standardization

Driven by the demand of higher bandwidth density in data center interconnect systems, optical switches and other interconnects, the evolution of various past, present and future form factor standards for optical transceivers shows irrespective of the specific application a clear trend towards smaller footprint, lower power consumption and higher optical performance. Figure 1 (Source: shows a selection of form factor pluggables.

Figure 1: Present and future optical interconnect form factors (Source:
Figure 1: Present and future optical interconnect form factors (Source:

To satisfy these demands and to enable smaller optical engines, photonic integrations lends itself as a potential solution. As observed in the world of electronics, where closer and closer integration offered huge benefits in all the important metrics, the same level of gain is expected from photonic integration. Certainly, we have seen in the very recent past an uptake of photonic integrated circuits (PICs) in the market []. However, despite early promises to enable large volumes of PICs at a low cost, the PIC market is driven by high-end devices. One might cite several reason, why that is the case, however, one major factor is the high initial cost associated with PICs: Up to 80% of cost in optical subassemblies is related to packaging, as no real standards – as e.g. for electronic ICs – are available to optical packaging. A second significant cost driver is related to the choice of materials in PICs: Certainly, for absolute lowest cost the preferred material is silicon. The availability of mature fabrication processes from the electronic IC industries, which produces enormous quantities of dies at remarkable yields, also allows for high volume and low cost manufacturing of photonic dies. However, the intrinsic properties of silicon (the indirect bandgap at telecom wavelength result in a quantum efficiency of around 10^-6) prevent it from efficiently emitting light. Light-emitting capabilities, however, are the major advantage of InP, a compound III-V semiconductor, which produces light very effectively at both important wavelength windows of 1.3 µm and 1.55 µm. Admittedly though, InP does not profit from mature manufacturing processes as seen in the silicon industry and is therefore more costly on a wafer and die level. Due to less reliable processes, which result in lower yields, smaller wafer sizes available and the need for more expensive hermetic packages, InP dies are generally more expensive than their silicon counterparts.

The DIMENSION projects aims to address all these challenges by combining the best properties of silicon with the light-emitting capabilities of InP. By integrating InP layers in the back-end of a CMOS compatible silicon photonic line, the shortcomings of silicon will be overcome and all functionality that is needed for an optical transceiver System on a Chip (SoC) will be made available on a single platform. Having electronic ICs, passive photonic ICs and active light sources on a single chip enables truly compact optical transceivers that easily fit any of today’s form factors and will ultimately result very high density optical transmission systems.

An application example is the Integrated Coherent Transmit Receive Optical Sub-Assembly (IC-TROSA) shown in Figure 2.

Figure 2: IC-TROSA Variant a (left): Non-hermetic, BGA mountable package. Variant b (right): Hermetic package with integrated laser.
Figure 2: IC-TROSA Variant a (left): Non-hermetic, BGA mountable package. Variant b (right): Hermetic package with integrated laser.

The OIF projects defines two variants of a board-mountable optical engine (BOE) for the use in coherent applications. The small footprint of both packages require photonic integration. Variant a (Figure 2, left) shows a non-hermetic package with a BGA connector on the bottom side aimed at silicon photonic applications, while variant b (Figure 2, right) is a hermetic package to be used with InP PIC and integrated laser source. Even though variant b is much larger compared to variant a, it is expected to feature a much lower level of integration as hermetic packages require much more space. Variant a, however, relies on an external laser, which is fiber coupled to the IC-TROSA and thus still requires additional space on the host PCB in addition to fiber routing in between. Applying the DIMENSION technology to this concept would allow vendors to build an IC-TROSA that exhibits all the benefits of variant a – BGA mounting, non-hermiticity, small footprint and a high level of integration, while additionally integrating a laser source without the need for additional external components and fiber routing. Such a device would easily enable very small form factor pluggables such as COBO, OSFP and even QSFP-DD to be used in coherent applications and thus significantly increase bandwidth density of data center interconnects and other similar applications. The added bonus of significant cost reduction together with higher bandwidth available to cloud based enterprises, ISPs and other businesses, is desperately needed to ensure tomorrow’s bandwidth intense applications and services can be provided to the end user.