Project Results

  • component designs
  • component fabrication
  • component measurements
  • development of the III-V on silicon technology
  • first wafer run of III-V and silicon components with the novel developed integration technology
  • techno-economic study of DIMENSION technology
  • dissemination, exploitation and standardization activities

…for more information, please see reports on deliverables page and publications.

…further project results will be published soon.

WP1 – Project management

Project meetings were organized. Furthermore, the mode of all-hands webconferences every three weeks was retained. The project webpage was continuously updated. A tool was implemented to record and analyze statistics of webpage visits. During the reported project period, 8 project deliverables and 2 milestones were achieved. Accordingly, deliverable reports have been prepared and submitted. All work packages are running. In principle DIMENSION has made good progress. However, due to faced technical challenges the project is delayed.

WP2 – System requirements, transceiver specifications and benefits evaluation

The work focused on the comparison of different transceiver designs and their possible implementation options. The transceiver solutions that are targeted in DIMENSION, were compared with several reference standard designs and technologies that are the basis of current commercially available 100G solutions and possible future alternative approaches for implementing 400G transceiver modules. The potential benefits from the introduction of the DIMENSION transceiver solutions in future data centers was explored. The different designs were first investigated through physical layer simulations in order to identify their transmission performance limits and subsequently they were compared in terms of their expected cost and power consumption performance. The aforementioned relevant investigations were presented in detail in D2.3 about techno-economic evaluation and power consumption study. Certainly, the monolithic integration approach targeted in DIMENSION is expected to have lower costs compared to hybrid solutions. The cost reduction will be associated mainly with the production of the chip, but will also drive down the costs of packaging and testing that are the prevailing ones in current implementations.

WP3 – Optical component design and fabrication

The development of further silicon photonics devices and III-V lasers continued. A III-V epitaxial layer stack was designed and optimized for the quantum well layer growth and the integration on silicon. Different approaches for current injection were investigated and different oxidation processes were developed. The fabrication of high quality silicon photonic components was optimized and an excellent yield was achieved. Furthermore, a robust planarization process was developed. With this the most important process of molecular wafer bonding could be successfully applied. Finally, the techniques and components were used for the first combined III-V on silicon wafer run.

WP4 – Electronic design and electro-optic integration

The design on integrated driver circuits and electro-optical devices led to first co-integrated modulator and driver structures which were fabricated with EPIC technology. Further designs include a PAM4 laser driver and PAM8 modulator driver which are still in fabrication. The development of the integration process has culminated in an EPIC mask-set design for the demonstration of III-V integration into the EPIC technology. Different approaches to achieve an efficient coupling between the III-V device and Si waveguide have been discussed and simulated. One promising approach of including an additional poly-silicon layer between the III-V laser and the Si waveguide has been selected as a path forward to lower the losses.

WP5 – Packaging and characterization and evaluation of demonstrators

Different setups and approaches for component characterizations were tested. This includes setups for laser characterization, such as current-power characteristics, wavelength-temperature characteristics as well as laser linewidth, and passive components. First electrical driver designs were successfully measured. Further optical coupling and characterization measurements were carried out for the first received EPIC samples. The complete measurement of the designed electro-optic devices was prepared and appropriate test-boards have been designed. The focus of the packaging research has been on optical coupling to the grating coupler as well as electrical wire bonding. For the latter best results have been observed for Al wedge bonding with softness and small diameter Au bond wires.

WP6 – Dissemination, Exploitation and Standardization

Many activities have been achieved. These involve: further project introduction at several workshops and conferences, project webpage with visitor statistics, scientific publications in journals and on conferences, the organization of workshops and information spreading via scientific social media like ResearchGate. In total we achieved 11 conference publications and 4 journal publications including one big review article in IEEE Communications Surveys & Tutorials. By the organization of two workshops, one on data center interconnect technologies and one together with other Photonics21 projects, during the “Photonics in Switching and Computing” (PSC) 2018 in Cyprus a fruitful exchange of knowledge and experience has been enabled. To secure the rights of DIMENSION’s key findings another patent has been filed on the epitaxial growth scheme for III-V fabrication on silicon. The standardization bodies for On-Board Optics (COBO) and OIF ‘IC-TROSA’ (Integrated Coherent Transmitter Receiver Optical Subassembly) have been further followed. Finally, a liaison between the COBO and IC-TROSA has been established. Last but not least, there have been two PhD students working on DIMENSION who finalized their dissertations with great success

Driven by the demand of higher bandwidth density in data center interconnect systems, optical switches and other interconnects, the evolution of various past, present and future form factor standards for optical transceivers shows irrespective of the specific application a clear trend towards smaller footprint, lower power consumption and higher optical performance. Figure 1 (Source: https://ethernetalliance.org/ea/) shows a selection of form factor pluggables.

Figure 1: Present and future optical interconnect form factors (Source: https://ethernetalliance.org/ea/).
Figure 1: Present and future optical interconnect form factors (Source: https://ethernetalliance.org/ea/).

To satisfy these demands and to enable smaller optical engines, photonic integrations lends itself as a potential solution. As observed in the world of electronics, where closer and closer integration offered huge benefits in all the important metrics, the same level of gain is expected from photonic integration. Certainly, we have seen in the very recent past an uptake of photonic integrated circuits (PICs) in the market [https://www.lightcounting.com/]. However, despite early promises to enable large volumes of PICs at a low cost, the PIC market is driven by high-end devices. One might cite several reason, why that is the case, however, one major factor is the high initial cost associated with PICs: Up to 80% of cost in optical subassemblies is related to packaging, as no real standards – as e.g. for electronic ICs – are available to optical packaging. A second significant cost driver is related to the choice of materials in PICs: Certainly, for absolute lowest cost the preferred material is silicon. The availability of mature fabrication processes from the electronic IC industries, which produces enormous quantities of dies at remarkable yields, also allows for high volume and low cost manufacturing of photonic dies. However, the intrinsic properties of silicon (the indirect bandgap at telecom wavelength result in a quantum efficiency of around 10^-6) prevent it from efficiently emitting light. Light-emitting capabilities, however, are the major advantage of InP, a compound III-V semiconductor, which produces light very effectively at both important wavelength windows of 1.3 µm and 1.55 µm. Admittedly though, InP does not profit from mature manufacturing processes as seen in the silicon industry and is therefore more costly on a wafer and die level. Due to less reliable processes, which result in lower yields, smaller wafer sizes available and the need for more expensive hermetic packages, InP dies are generally more expensive than their silicon counterparts.

The DIMENSION projects aims to address all these challenges by combining the best properties of silicon with the light-emitting capabilities of InP. By integrating InP layers in the back-end of a CMOS compatible silicon photonic line, the shortcomings of silicon will be overcome and all functionality that is needed for an optical transceiver System on a Chip (SoC) will be made available on a single platform. Having electronic ICs, passive photonic ICs and active light sources on a single chip enables truly compact optical transceivers that easily fit any of today’s form factors and will ultimately result very high density optical transmission systems.

An application example is the Integrated Coherent Transmit Receive Optical Sub-Assembly (IC-TROSA) shown in Figure 2.

Figure 2: IC-TROSA Variant a (left): Non-hermetic, BGA mountable package. Variant b (right): Hermetic package with integrated laser.
Figure 2: IC-TROSA Variant a (left): Non-hermetic, BGA mountable package. Variant b (right): Hermetic package with integrated laser.

The OIF projects defines two variants of a board-mountable optical engine (BOE) for the use in coherent applications. The small footprint of both packages require photonic integration. Variant a (Figure 2, left) shows a non-hermetic package with a BGA connector on the bottom side aimed at silicon photonic applications, while variant b (Figure 2, right) is a hermetic package to be used with InP PIC and integrated laser source. Even though variant b is much larger compared to variant a, it is expected to feature a much lower level of integration as hermetic packages require much more space. Variant a, however, relies on an external laser, which is fiber coupled to the IC-TROSA and thus still requires additional space on the host PCB in addition to fiber routing in between. Applying the DIMENSION technology to this concept would allow vendors to build an IC-TROSA that exhibits all the benefits of variant a – BGA mounting, non-hermiticity, small footprint and a high level of integration, while additionally integrating a laser source without the need for additional external components and fiber routing. Such a device would easily enable very small form factor pluggables such as COBO, OSFP and even QSFP-DD to be used in coherent applications and thus significantly increase bandwidth density of data center interconnects and other similar applications. The added bonus of significant cost reduction together with higher bandwidth available to cloud based enterprises, ISPs and other businesses, is desperately needed to ensure tomorrow’s bandwidth intense applications and services can be provided to the end user.

For further information on COBO and IC-TROSA, please refer to the Link page.